This invention relates to an apparatus for synchronizing video signals and in particular, to an interface which enables computer generated images and video controlled images to be simultaneously displayed on a monitor.
Television video pictures including video cassette and camera transmitted pictures are produced utilizing interlaced signals comprised of an odd number of scan lines. For example, in the United States 525 scan lines are utilized and in Europe 625 scan lines are utilized. The television image is divided into two equal fields containing one-half of the total number of scan lines of a frame. Therefore, in the United States, each field has 262.5 scan lines while in Europe, each field has 312.5 scan lines.
Similarly, computers output computer signals to display an image on a monitor utilizing scan lines. Synchronizing pulses are utilized to maintain both the television video (herein after "video") image and computer generated video (hereinafter "computer video") image properly displayed on the monitor. The monitor relies on receipt of synchronizing pulses. The synchronizing timing of computer signals and the video signals are not the same.
Computer video signals are utilized to emulate video signals for video synchronization such as computer generated overlays or the like. Proper emulation requires the computer controller to exhibit similar vertical timing corresponding to the number of scan lines used in the video signals. Since each television scan line must correspond to each computer controller scan line, timing corrections made to the computer controller must be accomplished during the vertical timing period. However, computer video signals cannot be outputted as half scan lines to correspond to the television video field.
Several systems are known in the art for altering the computer video signal vertical timing to emulate that of a television video signal. One such system is known from U.S. Pat. No. 4,670,785 issued to the applicant in which the computer video controller is programmed to display one scan line less than the television signal and then stopping the clocking signal for the controller to effect a delay of one scan line. This system has been satisfactory. However, it suffers from the disadvantage that during this time period, when the clocking system is stopped, the video controller's ability to receive or transmit data is impaired or defeated. This has the result of slowing the speed at which the video controller can accept data which is directly related to the speed at which it can display data on the monitor. This results in an overall degradation of the video controller's performance.
Additionally, these prior art devices have utilized several phase lock loop or other locking methods to obtain horizontal synchronization. One such method is providing clock pulses to the computer video controller at a multiple of the horizontal synchronization frequency as is taught in U.S. Pat. No. 4,346,407 issued on Aug. 24, 1982. A second method is to provide clock pulses to a computer video controller at a known frequency so that the computer video controller will create a frequency that is intentionally higher than the external video frequency allowing the removal of pulses to achieve synchronization as is taught in U.S. Pat. No, 4,670,785 issued on June 2, 1987. A third method known in the art is to provide clock pulses to the computer video controller at a multiple of the chroma burst frequency. These methods have also been satisfactory. However, they suffer from the disadvantage that each of these methods utilize a closed loop system with the computer video controller out of the loop. They utilize either phase lock loops or gated oscillators designed to run at fixed frequencies. They do not allow for any variability in the compensation to the synchronization process.
Accordingly, it is desired to provide an apparatus for synchronizing computer video signals with television video signals which does not retard the video controller's ability to receive or transmit data.